BCM2705 ? multimedia processor for mobile phone handsets BCM2705 block diagram ? very low power: mpeg-4 encode from only 10mw vga mpeg-4 encode/decode at 30 fps with audio 4 megapixel jpeg encode and decode ability to process raw bayer camera data 3gp and mp4 file streaming and mms support multiple format audio recording and playback drm ready 64 polyphony midi player and music synthesizer 640 kb of on-chip sram high quality graphics acceleration for 3d games sd, mmc, sdio, and memory stick interfaces 100% programmable forward-compatible with high-performance bcm2702 the BCM2705 is the world?s most power-efficient, high- performance mobile multimedia processor optimized for mobile phone handsets. based on videocore ? ii processor for maximum performance and software compatibility with the bcm2702. the BCM2705?s fully programmable architecture enables: a range of software multimedia functions greater flexibility improved time-to-market multimedia coprocessor: simplifies system partitioning allows the dsp core in the cellular baseband chipset to be optimized for modem function only. preserves software investment already made on baseband. pin-compatible with the advanced bcm2702: same package outline makes it interchangeable during development. broadcom provides all the necessary middleware and services for rapid and seamless integration with a host processor, as well as a complete developmen t kit with a fully featured toolchain for rapid development of applications. features summary of benefits audio audio in audio out debug b-scan camera 1 sdcard or mmc memory stick speaker mic i 2 s or pcm or ac?97 i/f memorystick pro i/f sdio i/f jtag multiformat raw/ccir601 camera i/f analog blocks including smps and pll 5 mb on-chip ram BCM2705 videocore ii with drm external memory i/f second external memory i/f i 2 c spi master uart gpio 8/16-bit parallel host interface bus bypass mode optional sdram rf keypad baseband flash/sram baseband main lcd sub-lcd optional flash camera 2
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2005 by broadcom corporation. all rights reserved. 2705-pb00-r 01/04/05 broadcom ? , the pulse logo, and connecting everything ? are trademarks of broadcom corporation and/ or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. specifications processor - 150-mhz dual-alu videocore ? ii - 128 kb instruction and data caches - 5 mb of on-chip sram serial interfaces - i 2 c master - spi master - uart for bluetooth ? , irda camera interface - programmable 8/16-bit cmos/ccd camera input port - supports up to two 4-megapixel image sensors - yuv ccir 601/656 - raw bayer rgb format (8/10/12/16-bit data) - windowing and subsampling functions - can be used to connect to mobile tv front end external memory/card interfaces - high-speed memory interface (connection to sdram, sram, flash and external peripherals) - secondary memory interface (e.g., for connection to memory- mapped lcd and external peripherals) - programmable chip select and address lines - memorystick pro? - sd, mmc, and sdio - support for nand/nor flash including boot-from-nand - high speed dma host interface - appears as memory-mapped peripheral to host - programmable industry-standard interfaces - 3 bit address and 8/16-bit data bus - dual software channel clock and power management - on-chip smps controller - four power modes: run, sleep, hibernate, and power-down - 0.8v - 1.2v core operation and 0.6v in hibernation mode - programmable i/o 1.5v - 2.8v - bypass mode allows host access to memory-mapped peripherals with BCM2705 in power-down - clock manager: three plls generate 195-khz ? 200-mhz clocks for external devices audio interfaces - ac '97 - i 2 s - pcm audio drm - drm-capable - unique chip id code - encrypted code with freely programmable key - cprm encryption for sd card, aes, 3des, rsa, etc. general purpose and debug interfaces - 30 pins of gpio - jtag and emulation interface for boundary scan technology - 281-pin tfbga package (10.1mm x 10.9mm) - 0.13 micron cmos display - support for multiple memory-mapped displays up to xga resolution - up to 24 bit internal precision (16m colors) - scalable image output with pixel level interpolation - configurable refresh rate
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